Data transfer schemes in 8085

At the time of executing one 8085 program, interruption can be done in the mid-way by the virtue of the program by an Input Output device. Interruption can be done by the method according to which the processor works, since it wants urgent communication with the processor. The data transfer schemes always want for sending information to the processor, rather receiving information from the 8085 processor. It is so because sending and receiving information in the entire 8085 data transfer scheme process plays a vital role for executing the entire program rather process.

The communication is not done directly with the Input Output device. The communication processes are carried out systematically by the help of Input Output device by the virtue of an Input Output port. The data transfer can be either in two forms namely parallel or serial respectively. By the virtue of the Programmed Input Access or rather transferring data in parallel the data transfer can be possible by using the Input Output programmed part or by Direct Memory Access (DMA) scheme. For transferring data in parallel we have three different ways by means of which microprocessor communicates with an Input or Output. They are:

  • Basic or simple data transfer scheme: The simplest data transfer scheme is the basic or simple data transfer. This method is beneficial to us when we have accurate know-ledge of the Input Output device timing characteristics.

  • Status check data transfer: Status check data transfer process is a much more complex process than simple data transfer. We use this method is used when there is lack of accurate knowledge of the Input Output device consisting of the timing characteristics. Status information is received by the processor regarding the readiness of the Input Output device for performing the data transfer.

  • Interrupt driven data transfer: We use this method when there lacks accurate knowledge of the timing characteristics of the Input Output device which takes maximum time for the device to be ready for use. Suppose we resort for the checking of data transfer; the processor here wastes a huge time in the loop for the device to get ready up to the mark.