Data Structure
Networking
RDBMS
Operating System
Java
MS Excel
iOS
HTML
CSS
Android
Python
C Programming
C++
C#
MongoDB
MySQL
Javascript
PHP
Physics
Chemistry
Biology
Mathematics
English
Economics
Psychology
Social Studies
Fashion Studies
Legal Studies
- Selected Reading
- UPSC IAS Exams Notes
- Developer's Best Practices
- Questions and Answers
- Effective Resume Writing
- HR Interview Questions
- Computer Glossary
- Who is Who
8255 Programmable Peripheral Interface Chip
Intel 8255 is a peripheral interface (PPI) chip which is programmable. It is used for the connection of peripheral devices and interfacing. We call Peripheral device also as Input Output device. We use Input Output ports for the connection of Input Output devices. Hence 8255 is a programmable Input Output port chip. It is a 40 pin chip available for dual line packaging. Power supply of +5 Volt DC is needed for its working. It consists of two programmable Input Output ports having of size 8 bits and two programmable Input Output ports of size 4 bits. We call them as Port A, Port B, Port C upper, and Port C lower, respectively. These pins source 1 mA of current at 1.5V, when they are programmed to work as the Output pins.
The pin diagram of 8255 is shown below −
We address Port C Upper and Port C lower such that they constitute a port of 8 bit uniquely. Hence we divide port C into 2 parts having 4 bits. Hence we program Port C lower as Input and Port C upper as Output.
The port selection logic is given where the output is set by us to the logic 1 and we reset it to logic 0.
There are three modes of operation performed by 8255 they are as mode 0, mode 1 and mode 2. We call the mode 0 as the simple Input Output or the basic Input Output for performing the simplest mode of operation. Every ports of 8255 can be programmed to work in mode 0. We call mode 1 as the strobed Input Output or handshake Input Output. It is useful when data is supplied to the input device by the microprocessor at irregular interval of time. Finally, when the data is read by the processor the port informs the Input device that the processors already read the data.
The following table depicts the how the port selection is being done in 8255.
| A1 | A0 | Port Selected |
|---|---|---|
| 0 | 0 | Port A |
| 0 | 1 | Port B |
| 1 | 0 | Port C |
| 1 | 1 | Control Port |
Also any line of Port C, which is programmed as output can be set to logic 1, or reset to logic 0 using the single bit set/reset feature of Port C also. This feature reduces software requirement in control-based applications. This facility is provided only for Port C. This feature is also used for enabling/disabling interrupts from 8255 ports.
The functionality of these three ports is decided by the contents of the control port. The control port can only be written by the microprocessor. Intel 8085 cannot read it. Thus, there are three ports which can be used for I/O operations, and a control port to control the function of these ports. A port inside the 8255 is selected for communication by the 8085 by the address-input pins A1 and A0, as shown in the above table. The direction of data transfer is dictated by the RD* and WR* input signals. Of course, the 8255 chip should be first of all selected by activation of CS* signal before a port inside 8255 can be selected. For example, the control port is written with the contents sent out by 8085 on D7-0 pins of 8255 when CS* = 0, WR* = 0, A1 = 1, and A0 = 1. Thus, A1 and A0 together with RD*, WR*, and CS* decide the manner in which 8085 communicates with 8255.
The 8255 can be connected in a microcomputer system as either memory-mapped I/O or I/Omapped I/O. Suppose we want 8255 connected as I/O-mapped I/O with addresses of Port A, Port B, Port C, and control port as 20H, 21H, 22H, and 23H, respectively. Then one of the possible chip select circuits is shown in the fig. In this figure A7-0 could have been used instead of A15-8.
Similarly, suppose we want 8255 connected as memory-mapped I/O with addresses of Port A, Port B, Port C, and control port as FFFCH, FFFDH, FFFEH, and FFFFH respectively. Then one of the possible chip select circuits is shown in the following fig. In this figure A7-0 is the LS byte of address generated using 8212 or 74LS373 as an address latch.
4K+ Views
