VLIW stands for Very-Long Instruction Word (VLIW) architectures. It is an appropriate alternative for exploiting instruction-level parallelism (ILP) in programs, especially, for performing more than one basic (primitive) instruction at a time.
These processors include various functional units, fetch from the instruction cache a Very-Long Instruction Word including various primitive instructions, and dispatch the whole VLIW for parallel implementation.
These capacities are exploited by compilers that produce code that has grouped separate primitive instructions executable in parallel. The processors have associatively simple control logic because they do not implement any dynamic scheduling nor reordering of operations.
The main goal of VLIW is to remove the complicated instruction scheduling and parallel dispatch that appears in most modern microprocessors. A VLIW processor should be quicker and less costly than a comparable RISC chip.
As shown in the figure, the multiple functional units share a common multi-ported register file for fetching the operands and storing the results. Parallel random access by the functional units to the register file is facilitated by the read/write crossbar. Execution of the operations in the functional units is carried out concurrently with the load/ store operation of data between a RAM and the register file.