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What is the layout of Pipelined Instruction in computer architecture?
Pipelined instruction processing covers two key elements as the specification, or logical layout, and the implementation of instruction pipelines. The logical layout determines the tasks to be adept. It consists of the declaration of the pipelines to be executed and for each of the pipelines a detailed specification of the subtasks to be implemented and their execution sequence.
In current processors, multiple pipelines are declared for each of the main instruction classes. There are generally independent pipelines for the processing of FX and logical data, known as the FX pipeline, for FP data, the FP pipeline, for loads and stores, the L/S pipeline, and finally, for branches, the B pipeline.
The detailed specification of a pipeline contains the statement of the pipeline stages and the specification of the subtasks to be completed in each of the stages.
Logical pipelines can be performed in several methods such as either by using a similar hardware pipeline for all logical pipelines or by executing each logical as a dedicated pipeline.
Three important methods have to be treated, as displayed in the figure. These elements are the layout and the multiplicity of the physical pipelines, and how sequential consistency is continued in the case of multiple physical pipelines.
First, let us consider the layout of the ‘physical’ pipelines with mention to the following diagram, the main point is whether the logical pipelines should be executed with minimal hardware, by a multifunctional pipeline, or be execution-oriented, by using multiple dedicated pipelines.
Multifunctional pipelines are concerned, there is only one published design where all the FX, FP, L/S, and B instructions (branch instructions) are processed using a similar physical pipeline. This design is the MIPS R4200, introduced in 1994. By contradiction, executing FX, L/S, and B instructions on the equal pipeline is a usually employed ‘classical’ approach, the master-pipeline approach.
Therefore, the adder of the FX pipeline is also used for the address calculations required when implementing L/S and B instructions. Therefore, each major instruction class is executed in the same pipeline by executing the given subtasks in the denoted sequence. Otherwise, dedicated pipelines can also be performed. The motivation is to improve performance by having multiple, specialized pipelines operating in parallel.
There are three methods is required for the preservation of sequential consistency in the case of multiple pipelines are as follows −
In the first method, it can consider having a multifunctional pipeline for FX, L/S, and branch instruction and a distinct FP pipeline. Therefore, the FP pipeline is not enabled to write back the results into the register file or memory independently.
In the second method, it can consider two lock-stepped operating pipelines, a master FX and an FP pipeline. Therefore, in-order completion of the instructions is accomplished by accurately lengthening the shorter FX pipeline, by learning unused cycles (bubbles) into it, if required.
The third method is reordering. It is generally used if there are more than two pipelines. By reordering, the pipelines are not enabled to write back the results directly into the architectural registers or into memory.
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