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What is Switch-based Interconnection Networks in Computer Architecture?
In this type of network, connections among processors and memory modules are made using simple switches. There are three basic interconnection topologies such as crossbar, single-stage, and multistage.
A crossbar network defines the other extreme to the limited single bus network. While the single bus can provide only a single connection, the crossbar can provide simultaneous connections among all its inputs and all its outputs. The crossbar includes a switching element (SE) at the intersection of any two lines extended horizontally or vertically inside the switch.
In this case, a single stage of switching elements (SEs) exists between the inputs and the outputs of the network. The simplest switching element that can be used is the 2 x 2 switching element (SE). There are four possible settings that an SE can assume. These settings are called straight, exchange, upper-broadcast, and lower-broadcast.
In the straight setting, the upper input is transferred to the upper output and the lower input is transferred to the lower output. In the exchange setting the upper input is transferred to the lower output and the lower input is transferred to the upper output.
In the upper-broadcast setting, the upper input is broadcast to both the upper and the lower outputs. In the lower broadcast the lower input is broadcast to both the upper and the lower outputs.
It can establish communication between a given input (source) to a given output (destination), data has to be circulated several times around the network. A well-known connection pattern for interconnecting the inputs and the outputs of a single-stage network is the Shuffle –Exchange.
Multistage interconnection networks (MINs) were introduced as a means to improve some of the limitations of the single bus system while keeping the cost within an affordable limit. The most undesirable single bus limitation that MINs is set to improve is the availability of only one single path between the processors and the memory modules. Such MINs provide some simultaneous paths between the processors and the memory modules.
A general MIN consists of several stages each consisting of a set of 2 2 switching elements. Stages are connected using the Inter-stage Connection (ISC) Pattern. These patterns may follow any of the routing functions such as Shuffle –Exchange, Butterfly, Cube, and so on.
This network is known as the Shuffle –Exchange network (SEN). The settings of the SEs how several paths can be established simultaneously in the network.
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