Multiport memory is a memory that helps in providing more than one access port to separate processors or to separate parts of one processor. A bus can be used to achieve this kind of access.
This mechanism applies to interconnected computers too. A multiport memory system uses separate buses between each CPU and each memory module.
Each processor bus is linked to each memory module. A processor bus includes three components as an address, information, and control lines. These components are required to connect with memory. The memory module has four ports and each port includes one of the buses.
A module should have internal control logic to check which port will have an approach to memory at any defined time. It can be assigning constant priorities to each memory port supports in resolving memory access conflicts.
The priority for memory access associated with each processor is generated with the physical port position that its bus appears in every module. Consequently, CPU1 has priority over CPU2, CPU2 has priority over CPU3, and CPU4 has the least priority.
The multiport memory organization has the advantage of a high transfer rate. This is because of several paths between memory and processors.
The only drawback is that it needs expensive memory control logic and more cables and connectors. Hence, this interconnection architecture is generally suitable for systems having a tiny number of processors.