What is logical layout of FX Pipelines in Computer Architecture?

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A logical layout of an FX pipeline consists, first of the specification of how many stages an FX pipeline has and what tasks are to be performed in these stages. The other key aspect of the design space is how FX pipelines are implemented. FX pipeline can be interpreted in both a broader and narrower sense.

In the broader sense, it covers the full task of instruction fetch, decode, execute and if required writeback. In this case, it is usually also employed for the execution of L/S and branch instructions and is termed as master pipeline.

In the narrower sense, an FX pipeline is understood to deal only with the execution and writeback phases of the processing of FX instructions. Then the preceding task of instruction fetch, decode and in the case of superscalar execution, instruction issue are performed by a separate part of the processor.

Integer and Boolean instruction account for a considerable proportion of programs. Together, they amount to 30-40% of all executed instructions. Therefore the layout of FX pipelines is fundamental to obtaining a high-performance processor.

In the following, we describe the FX pipelines for RISC and CISC processor separately, since each type has a slightly different scope. While processing operate instructions, RISC pipelines have to cope with register operands. By contrast, CISC pipelines must be able to deal with both registers and memory operands as well as destination.

RISC Pipelines

A traditional FX pipelines in RISC processor is modelled on the execution of register-register instructions. Consider here that the execution of register-register instructions includes the following subtasks −

  • Fetch the instruction
  • Decode the instruction
  • Fetch the referenced registers
  • Execute the specified operations
  • Write-back result into the register file

The Sparc, SuperSparc, MC88110 and the PowerPC are examples of RISC processor which use this arrangement for FX Pipelines. In certain processors there are some minor variations in cycle durations such as in the MC 8810 pr SuperSparc processor as shown in table.

Variations in Pipeline Cycle duration in traditional FX Pipelines


FetchDecodeExecuteWriteBack
Most Processors1111
MC 881101½1½
SuperSparc13/21½

CISC Pipelines

CISC Pipelines differ from RISC Pipelines, mainly in that CISC pipelines must be able to process both register and memory operands and destinations.

In order to access a memory operand (which is supposed to be in the cache), two additional subtasks are carried out − calculating the operand address and fetching the operand (presumably from the cache).

Therefore, a traditional CISC Pipeline, which is laid out to execute register-memory instructions effectively, contains two more stages than a traditional RISC pipeline. Pipeline consists of the following six stages are instruction fetch (F), decode (D), address calculation (A), cache access (C), execute (E) and writing back the result into the register file (WB). It is used by several CISC processor such as the MC 68040 and MC 68060.

The pipeline can also be easily used to execute register-register and load/store instructions. In order to execute register-register instructions, the referenced register operands are fetched in the D cycle, while the A and C cycles remain unused. Subsequently, the required operation is performed in the E cycle, and the result is written back into the register file during the concluding WB cycle.

raja
Updated on 20-Jul-2021 07:36:38

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