Both the pins RST5.5 and RST6.5 pins are inputs which are level sensitive. RST6.5 is of higher priority than RST5.5 but the pin RST5.5 is of higher priority than INTR. RST5.5 and RST6.5 have similar functions. The point to be noted that these pins must remain high till the 8085 checks all the internal interrupt signals at the end of the instructions. As we can easily see from the Fig. We activate the RST5.5 and RST6.5 internal interrupt signals if and only if when the external interrupt pins are in logic 1 state;
Flip-flop IE is in logic 1 state;
SIM instructions do not mask these interrupts.
The interruption of 8085 occurs because of RST5.5 or RST6.5 pin, only if the following conditions are satisfied:
Either RST5.5 or RST6.5 internal interrupt signal is in active state;
Interrupt signals of higher priority are not active.
If the above conditions are not satisfied even though the pins RST5.5 or RST6.5 are activated, interruption of 8085 does not occur.
The vectored interrupts of 8085 are RST5.5 and RST6.5. We have 5.5 * 8 = 002CH for RST5.5 and 6.5 * 8 = 0034H for RST6.5.