Let us say that the 8085 which is interrupted because of RST6.5 pin and has been branched to the ISS for the pin RST6.5. Then, except the DI instruction at the beginning of this ISS, all the interrupts gets disabled except TRAP. So, even if RST7.5 pin is in activated state in the middle of the execution of RST6.5 ISS, the interruption of 8085 will not occur due to RST7.5. Actually a higher priority interrupt is RST7.5, but the lower priority interrupt ISS cannot be interrupted by it of RST6.5. We solve this problem by specifically having the instruction which is EI at the ISS beginning for the pin RST6.5. Now RST6.5 ISS can be interrupted by but the problem lies in the fact that RST5.5 can also interrupt the RST6.5 ISS!
This is solved by the masking of the interrupts. It provides the ability for selectively disabling the interrupts. An interrupt pin which is already masked cannot interrupt, even though the interrupt pin is still in active state and the interrupts which are generally enabled using the EI set of instructions.