Let us consider the instruction to be executed as “MOV A, C”. Here in this case the value of 8 bit in the register C must be moved to the register. The given set of registers namely B, C, D, E, H, and L must be connected to the internal bus by means of a multiplexer (many input but only one output) or demultiplexer the reverse of multiplexer. The register meant to carry the work selects the specific unit and sends the appropriate code to the multiplexer such that the contents of register C are sent out to the multiplexer through the internal bus. The data from the internal bus is thereafter received by the Accumulator.
Let us consider the entire execution process of the given instruction “MOV D, A”. Here in this case, the bit value of the Accumulator gets moved to the register D. The bit value of 8 is sent to the accumulator. The registers B, C, D, E, H, and L are connected to the internal bus through a multiplexer/demultiplexer. The given register selects the unit for the appropriate code to the demultiplexer such that the register named D receives all the contents from the internal bus to the demultiplexer. Actually the basic concept lies in the fact that in the multiplexer many inputs merges to form one output. Whereas the reverse process is applicable for the demultiplexer. Hence in the address buffer we find The operations of arithmetic and logical sequence carried out involves two operands, among which one is operand is provided by the accumulator, and the other operand is provided by the Temp register. For example, in the addition process the instruction to the B register, all the contents are deliberately moved to the Temp register and then ultimately the Arithmetic Logical Unit performs the addition of register A and Temp register. In similarity with the W and Z