Implied addressing mode in 8085 Microprocessor

In 8085 Instruction set, there is one mnemonic XCHG, which stands for eXCHanGe. This is an instruction to exchange contents of HL register pair with DE register pair. This instruction uses implied addressing mode. In the instruction, we don’t mention as “XCHG HL, DE”. It is implied that it will deal with HL and DEregister pairs. So we write only XCHG as mnemonic. That’s why it is called an implied addressing mode. As it is 1-Byte instruction, so It occupies only 1-Byte in the memory. After execution of this instruction, the content between H and D registers and L and E registers will get swapped respectively. 

Let us suppose, HL and DEregister pairs are having ABCDH and 6789H contents respectively. After execution of instruction XCHGthe contents of HL and DS register pairs will be 6789H and ABCDH respectively. Here is the content training table for the better understanding – 

Let us see the timing diagram of this instruction XCHG as below –

Summary  − So this instruction XCHG requires1- Byte, 4-Machine Cycles (Opcode Fetch) and 4 T-States for execution as shown in the timing diagram.