There are various characteristics of CMOS which are as follows −
Noise Margin − The noise margin of CMOS logic ICs is significantly greater than that of TTL ICs. These circuits are available with a broad supply voltage range and the noise margin improves with the supply of voltage VCC.
The noise margin of CMOS is roughly 0.45 VDD. If the operating voltage is 12 V, the noise margin will be 5.4V. This implies that the connecting link between the driver and the load will not be affected by the noise interference unless the peak value of the noise picked up exceeds 5.4V. As a result, these devices are relatively immune to undesirable switching due to noise pickup.
Power Supply Requirement − CMOS devices can work over a fairly large voltage range that extends from 3V to 15V, which is not the case with TTL devices. The power dissipation level increases with the supply voltage.
Propagation Delay − Generally propagation delay time for CMOS is higher than that of TTL devices and varies from about 25ns to 100ns. Cascading of CMOS devices further adds up to the propagation delay. It can increase the operation speed device should be operated at higher supply voltages and reducing load capacitance. Propagation delay time tpLH≈tpHL≈30 ns and rise and fall times in CMOS gates are ≈60ns.
Power Dissipation − The average or static power dissipation of a CMOS device is around 10 mW. It can increase whenever there is a change from HIGH to LOW or LOW to HIGH state and the magnitude of increase depends on the frequency of operations i.e., with the switching speed. At 1 MHz the dissipation of power increases to 1 mW. Power dissipation is also based on capacitive loads.
Floating Inputs − In the case of TTL devices a floating or open input is equivalent to a high input. Hence a floating input in the CMOS gate is very susceptible to noise picked up given the high input impedance of the gate. This causes an increase in power dissipation.
Wired-logic − In case if the output of two inverter CMOS gate is connected, a large current will flow and will make the output ~VDD/2, which cannot be represented as state 1 or 0 resulting in the male function of the circuit and also the large current may damage the transistor. Hence, wired logic should not be used for CMOS devices. CMOS gates with open-drain output are available which can wired-AND operation. In this method, the drain terminal of the N-channel MOSFT is available outside and the load register is to be linked externally because the P-Channel load does not appear.