Discuss the MultiLevel Interrupts in Computer Architecture?

Computer ArchitectureComputer ScienceNetwork

In multilevel interrupts, more than one interrupt pin is present in the processor. Hence, interrupts can be recognized by the CPU on getting an interrupt request from some of the interrupt pins.

The figure shows the multilevel interrupt system.

Let us now discuss the process flow of a multilevel interrupt. When the external asynchronous input is inserted, the logic control of a multilevel interrupt is as follows −

  • The processor completes its current instruction.
  • The current contents of the program counter are stored in the stack.
  • The program counter is loaded with the address of an interrupt service routine.
  • Program execution reaches with the instruction taken from the memory location pointed by the new program counter contents.
  • The interrupt program is executed until a return instruction is executed.
  • Once the RET instruction receives the old address from the stack, it puts back the address into the program counter. This allows the interrupted program to continue executing the instruction following the one where it was interrupted.
raja
Updated on 27-Jul-2021 13:50:30

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