Let's discuss the Following two applications
Low order address latch
Output port which is interrupting.
Intel 8212 as low-order address latch − Here the low-order address lines and data lines are multiplexed and are available as AD7-0. It is convenient to have the address as many times and the separation of data on the different lines. Let's for an example, if we connect a chip like 2716 in an 8085-based system, the 2716 needs bit address of11 bits in its address pins, and here is separate 8 pins kept for data. Now connecting the AD7-0 pins of 8085 to the LS 8 address pins of 2716, the address will only be available for the only one clock cycle in a complete machine cycle. Thus, de-multiplexing of address and data is needed
Intel 8212 as an interrupting output port − When any output device wants to perform the driven interrupt data transfer, a positive pulse is send on the STB pin.
Transition which is High to low is based on STB results that helps in the activation of INT*. This results in the interruption of 8085 on the lines of RST5.5. Now the Program control is transferred to the location 5.5 * 8. Here we have an instruction to directly go to 2600H. Hence 2600H the ISS for RST5.5 is started immediately without delay.