We have assumed that the interrupt system gets enabled by using the EI instruction, and the signals which have higher priority are not in active state.
In the penultimate clock cycle of the last machine cycle of every instruction, the 8085 senses all the internal interrupt signals.
If the INTR internal signal which is at logic 1, the 8085 enters to a machine cycle which is called interrupt acknowledge (INA) machine cycle.
The interrupts from the Input Output port gets acknowledged by the 8085 by the activation of INTA* pin in the T2 state of the machine cycle INA where INTA* is a pin which is in active low state.
In the machine cycle which is M2 the least significant bit of ISS address gets transferred to the register Z of 8085 by means of 8259.
In M4 the MW machine cycle, Most Significant Byte of the Personal Computer is pushed to the stack.
In M5 the MW machine cycle the Least Significant byte of the Personal Computer is pushed to the stack.