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8212 Non-Programmable 8-Bit I/O Port
There are two types of Input Output ports. They are Programmable Input Output ports and Non-Programmable Input Output ports. Since the functions of Programmable Input Output ports changed by software they became more popular. We don’t need to change the wiring rather the hardware of the I/O port to change the function. Intel 8255 is a popular Input Output chip based on port. Whereas the I/O ports which are non-programmable needs to change the wiring or the hardware to change its complete function. We will see in later that the connection needs to be changed when 8212 works like an input port in place of output port. These Input Output ports which are non-programmable are designed in a simple way.
We find 8212 available in nowadays as a package chip which is dual in line having 24 pins total. We find its functional pin diagram below.
Voltage of + 5 V is required for it to work based on the supply which is DC. The latch which is 8 bit in 8212 receives the information which is present on the eight data inputs ranging from DI7 to D10. The condition which helps in information latching is present on DI7 to DI0 depends on the state of logic of the pin which is of mode MD. The information which is present in the latch comes out on the data output pins ranging from D7-D0. The condition which is satisfied for the information to be latched comes out is dependent MD pin.
We find 8212 available in nowadays as a package chip which is dual in line having 24 pins total. We find its functional pin diagram below.
Voltage of + 5 V is required for it to work based on the supply which is DC. The latch which is 8 bit in 8212 receives the information which is present on the eight data inputs ranging from DI7 to D10. The condition which helps in information latching is present on DI7 to DI0 depends on the state of logic of the pin which is of mode MD. The information which is present in the latch comes out on the data output pins ranging from D7-D0. The condition which is satisfied for the information to be latched comes out is dependent MD pin.
We have D-type flip-flop which is edge-triggered depends on 8212. We call it the service request flip-flop. It is responsible for generating an interrupt request on the pin INT*. INT* is an active low output pin, which is useful in interrupt-driven data transfer scheme. The internal architecture which is responsible for activating the INT* signal is shown below
The internal chip select signal gets activated when DS1* is 0 and DS2 is 1.
When a high to low transition is done by STB so that the internal signal which is SQ is 0.
Fig: Connection details for a flip flop latch in 8212
The following conclusions which are drawn from the fig shows that. When MD is equal to 1, CS acts latches for clock. When MD is equal to 0, STB acts as the clock for the latches. When the clock is in high state, the output Q of the latch follows input corresponding DI. When the high to low transition is made by the clock, latching of the data gets into action. The data at the output Q gets out on the pin corresponding DO when the EN signal gets activated. The EN signal gets activated whenever CS is equal to 1 or MD is equal to 1.
In brief lets gets the outline of the pins:
| Vcc: | Always gets connected to the dc corresponding to +5V |
| Gnd | Gets connected to ground |
| MD | It is the Mode input pin. determines the clock sources to latches. If MD is 0, STB acts as the clock input to the latches. If where as if MD is 1, CS acts as the input of the clock. |
| STB | It is Strobe input. |
| DS1*, DS2 | These are the devices which select pins. |
| DI7-0 | These are the eight Data inputs ranging from D7 to D0. |
| DO7-0 | Data outputs. |
| INT* | It is the Interrupt output pin which is Used for interrupting the microprocessor. |
| CLR* | It is an asynchronous clear input which is actively low. |
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