Instruction type DAD SP in 8085 Microprocessor


In 8085 Instruction set, DAD SP instruction is a special case of DAD rp instruction. In this instruction contents of HL and SP will get added and sum thus produced will get stored onto HL register pair. It occupies only 1-Byte in memory.

Mnemonics, Operand Opcode(in HEX) Bytes
DAD SP 39 1

Let us discuss about this instruction execution with one example. We are considering that HL and SP registers are having initial contents as 4050H and 5050H. So after execution of DAD SP instruction, the addition result will be 90A0H which will get stored on the HL register pair. Here is the tracing table below for better understanding.

Before After


5050H 90A0H


4050H 4050H


Any values Cy=0, No change in other flag bits

Address Hex Codes Mnemonic Comment
2006 39 DAD SP HL ← HL – SP

The timing diagram against this instruction DAD SP execution is as follows −


Summary − So this instruction DAD SP requires 1-Byte, 3-Machine Cycle (Opcode Fetch, Bus Idle, Bus Idle) and 10 T-States for execution as shown in the timing diagram.The opcode fetch cycle takes 4 T states and the remaining 6 T states, divided into two Machine Cycles, are for the instruction execution. During these 6 T (two Machine Cycles) states no bus operations are performed. Hence they are called bus idle Machine Cycles. During this ALE, RD etc. are not activated.

Published on 05-Dec-2018 10:53:56