Memory Write (MW) machine cycle in 8085 Microprocessor

In the last three clock cycles the instructions ‘MVI M, 25H’ are the example for Memory Write machine cycle. We have shown the Waveforms for MW machine cycle are shown in fig below.

The address which is sent out from the register pair in a Memory Write machine cycle is completely dependent on the MW machine cycle under the consideration as it is shown in the chart below.

Here is the detailing of the instruction execution –

In 8085 Instruction set, this instruction MVI M, d8 is used to load a memory location pointed by HL pair with an 8-bit value directly. This instruction uses immediate addressing for specifying the data. It occupies 2-Bytes in memory.

As an example, we can consider MVI M, ABH as an example instruction of this type. It is a 2-Byte instruction, with opcode for MVI M using up one Byte, and ABH using up another more Byte. We are considering that HL register pair is containing 16-bit address 4050H and content of that address initially CDH. So after execution of the instruction the updated values will be -

Table is Shown Below

Let us check the timing diagram of this instruction MVI M, ABH

Summary: So this instruction MVI M, ABH requires 2-Bytes, 3-Machine Cycles (Opcode Fetch, Memory Read, Memory Write) and 10 T-States for execution as shown in the timing diagram.