Clock Domain Crossing and Verification Course
Learn everything about CDC
Lectures -16
Duration -1.5 hours
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Course Description
Learn Clock Domain Crossing (CDC) design and verification concepts deeply by vlsideepdive.
We are on a mission to inspire and develop people to achieve their goals in professional life. We enable people to learn deeply through bite-sized, interactive learning experiences. Our courses are structured and designed by leading experts in their respective fields.
Industry Expert: Vikas Sachdeva (Vikas Sachdeva is a semiconductor design professional with more than 17 years of experience in the VLSI Industry. Vikas manages everything related to CDC products at Real Intent. He has multiple published papers and 2 patents in CDC. )
The course covers the following topics in CDC
Synchronous and Asynchronous Clocks
Metastability
Synchronizers
MTBF
Effects of Metastability
Glitch on Synchronizers
Pulse Width on Synchronizers
Open and Closed Loop synchronizers
Passing multiple signals across clock domains
Counters
Data path synchronization
FIFOs
Reset Paths
CDC Verifications steps
Learn deeply
vlsideepdive replaces traditional books & lecture videos with hands-on, interactive lessons. It’s a better (and more fun) way to learn.
For any experience level– Get started as a beginner with the fundamentals, or deep-dive right into advanced concepts. We have courses for ambitious people of all experience levels.
Master essential concepts – Build confidence with hands-on learning. You will get to see concepts visually, interact with the key ideas and solve challenging problems that get you to really think and learn deeply.
Stress less, learn better – Enjoy fun storytelling, guided problem solving, here your natural curiosity will automatically drive you.
Who this course is for:
- VLSI Designers
Goals
The course covers all the basic concepts in clock domain crossings (CDC) analysis
Understand how to avoid metastability in presence of Asynchronous clocks
Understand how avoid correlation loss across synchronizers
Understand design of FIFOs
Prerequisites
Basic knowledge of flop-flops and clocks
Curriculum
Check out the detailed breakdown of what’s inside the course
Introduction
1 Lectures
- Introduction 00:55 00:55
Synchronous and Asynchronous Clocks
1 Lectures
Metastability
1 Lectures
Synchronizers
1 Lectures
MTBF
1 Lectures
Synchronizer Deepdive
1 Lectures
Effects of Metastability
1 Lectures
Glitch on synchronizers
1 Lectures
Pulse width on synchronizers
1 Lectures
Open and closed loop synchronizers
1 Lectures
Passing multiple signals between asynchronous clock domains
1 Lectures
Synchronize counters
1 Lectures
Datapath synchronization
1 Lectures
FIFOs
1 Lectures
Reset paths
1 Lectures
CDC verification
1 Lectures
Instructor Details
Vikas Sachdeva
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