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Computer Science Articles
Page 36 of 53
What are the types of issue blockages in computer architecture?
The handling of issue blockages can be broken into two types as displayed in the figure. The first aspect called preserving issue order specifies whether a dependent instruction blocks the issue of subsequent independent instructions in the issue window. The second aspect is the alignment of instruction issue. It decides whether a fixed or gliding issue window is used.As shown in the figure, if a dependent instruction such as instruction b, blocks the issues of all subsequent instructions until the dependency is resolved, the issue order is known as ‘in-order’.However, restricting subsequent independent instructions from the issue can extremely disrupt ...
Read MoreWhat is the design space of Issue Policies?
Superscalar instruction issue is the most sensitive task of superscalar operation. The issue policy determines how dependencies are managed during the issue process. The issue rate defines the maximum number of instructions a superscalar processor can issue in each cycle.The design space of issue policy is complex. As shown in the figure, it consists of four major aspects. The first two define how false data and unresolved control dependencies are coped with during instruction issues. In both cases, the design options are to prevent them during instruction issues by using register renaming and speculative branch processing.The third condition decides whether ...
Read MoreWhat is Parallel Decoding in Computer Architecture?
A scalar processor has to decode only a single instruction in each cycle as shown in the figure. In addition, a pipelined processor has to check for dependencies to decide whether this instruction can be issued or not. In comparison, a superscalar processor has to perform a much more complex task.As shown in the figure, it has to decode multiple instructions, say four, in a single clock cycle. It also needs to check for dependencies from two perspectives: First, whether the instructions to be issued are dependent on the instructions currently in execution. Second, whether there are dependencies among the ...
Read MoreWhat are the key elements of Superscalar Processor?
Superscalar processing can be broken down into several particular tasks, which is shown in the figure. Superscalar processors can issue multiple instructions per cycle, the first task certainly is parallel decoding.Decoding in superscalar processors is a significantly more complex task than in the case of scalar processors and evolves into even more sophisticated as the issue rate improves.Higher issue rates can immensely extend the decoding cycle or can provide growth to various decoding cycles unless decoding is increased. An increasing technique of improvement is pre-decoding.This is partial decoding implemented in advance of typical decoding, while instructions are loaded into the ...
Read MoreWhat is Computer Architecture as a Multilevel Hierarchical Framework?
The concrete architecture at a given level is normally defined in the phrase of its components. Hence, the description of the concrete architecture at a given level is based on the abstract architectures of its components.As an effect, the concrete architecture at a specific level is a description at a higher abstraction level than the corresponding abstract architecture at the subsequent lower level.Thus, we can define that the sequence of theory of concrete and abstract architectures at successive levels yields a description framework at following higher levels of abstraction.Therefore, the three-level architecture description design considered, with independent concrete and abstract ...
Read MoreWhat are the interpretations of the theory of computer architecture?
It can interpret the theory of computer architecture at several levels of rising abstraction. At each level, the architecture will be represented by declaring the underlying computational model, the functional specification, and the actual implementation. Therefore, the interpretation covers three elements including the underlying computational model, the level of consideration, and the scope of interest, as displayed in the figure.First, it can overview the underlying computational model. Several years in the past, the term ‘computer architecture’ was inherently interpreted as a von Neumann architecture.Subsequently, when novel architectures that depend on a model of computation other than the von Neumann model ...
Read MoreWhat is Von-Neumann Model?
Von Neumann’s model is composed of three specific components (or sub-systems) including a central processing unit (CPU), memory, and input/output (I/O) interfaces. The figure defines one of the various possible methods of interconnecting these components.CPU − CPU can be regarded as the soul of the computing system, includes three main components: the control unit (CU), one or more arithmetic logic units (ALUs), and multiple registers. The control unit decide the order in which instructions should be implemented and controls the retrieval of the useful operands. It defines the instructions of the machine.The execution of each instruction is persistent by a ...
Read MoreWhat are the basic computational models?
There are six basic computational models such as Turing, von Neumann, dataflow, applicative, object-based, predicate logic-based, etc. These models are known as basic models because they can be declared using a basic set of abstractions.A hierarchy of subclasses can be defined for each of the basic models to any extent required. For instance, if the process abstraction is introduced into the von Neumann model, new subclasses can be defined according to whether all processes might have access to a global data space (Shared-memory subclass) or the processes could have their own local data spaces, and access remote data spaces by ...
Read MoreWhat are the relationships between programming languages and parallel architectures?
The theory of a computational model is a higher-level abstraction than the approach of programming language and computer architecture.A programming language can be speculation as a specification device making applicable the system of a computational task whereby a specific computational model is pretended.Computer architecture can be considered upon as a tool to execute a computational model or to implement a given computational task defined using a programming language, whereby a specific computational model is given.To demonstrate these relationships it can consider the basic features of the programming languages and computer architectures that compare to the von Neumann computational model.A programming ...
Read MoreImplementation of Global Instruction Scheduling in computer architecture
The implementation of global instruction scheduling is a technique called trace scheduling. Trace scheduling was first employed in the Bulldog compiler, developed for the experimental VLIW machine ELI-512 at Yale (Fisher et al, 1984), and subsequently in the Trace scheduling compiler of the commercial TRACE family of VLIW machines (Colwell et al, 1987).A more recently published novel global schedule technique is FRGS (Finite Resource Global Scheduling), developed and experimentally implemented by IBM for VLIW and superscalar processor (Moon and Ebcioglu, 1992, Moon et al, 1993).Trace SchedulingThis technique originates like most instruction scheduling techniques, in the schedule for horizontally microcoded machines ...
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