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Computer Architecture Articles
Page 16 of 26
What is the configuration of memory subsystem in computer architecture?
There is the following technique for joining memory chips to form a memory subsystem. Two or more chips can be combined to generate a memory with more bits per location. This is done by linking the corresponding address and control signals of the chips and linking their data pins to various bits of the data bus.For example, two 8 x 2 chips can be combined to generate an 8 x 4 memory as displayed in the figure. Both chips get the equal three address inputs from the bus, and the same chip enables and output enables signals.The data chips of ...
Read MoreWhat is internal chip organization in computer architecture?
The internal organization is linear. This chip has three address inputs and two data outputs, and 16 bits of internal storage constructed as eight 2-bit locations. The three address bits are decoded to choose one of the eight locations, but only if the chip enable is active. If CE = 0, the decoder is disabled and no location is selected.The tri-state buffers for that location’s cells are enabled, authorizing data to move to the output buffers. If both CE and OE are set to 1, these buffers are enabled and the data is output from the chip, therefore, the outputs ...
Read MoreWhat are Instruction Cycles in computer architecture?
The instruction cycle is the process a microprocessor goes through to process an instruction. First, the microprocessor fetches or reads, the instruction from the memory. Therefore it decodes the instruction, determining which instruction it has fetched. Finally, it implements the operations required to execute the instruction. Each of these functions including fetch, decode and execute contains a sequence of one or more operations.First, the microprocessor locates the address of the instruction on the address bus. The memory subsystem inputs this address and decodes it to access the desired memory locations. After the microprocessor enables ample time for memory to decode ...
Read MoreWhat is System Buses?
A bus is a set of wires. The elements of the computer are linked to the buses. It can transfer data from one element to another, the source element outputs data onto the bus. The destination element then inputs this information from the bus. As the complexity of a computer system improves, it becomes more effective (in methods of minimizing connections) at using buses instead of a direct connection between each pair of devices.Buses use less area on a circuit board and need less power than a huge number of direct connections. It can also need fewer pins on the ...
Read MoreWhat is Magnetic Tape?
Magnetic tape transport includes the robotic, mechanical, and electronic components to support the methods and control structure for a magnetic tape unit. The tape is a layer of plastic coated with a magnetic documentation medium.Magnetic tapes are used in most organizations to save data files. Magnetic tapes use a read-write mechanism. The read-write mechanism defines writing data on or reading data from a magnetic tape. The tapes sequentially save the data manner. In this sequential processing, the device should start searching at the starting and check each record until the desired information is available.Magnetic tape is the low-cost average for ...
Read MoreWhat are Magnetic Disks?
A magnetic disk is a storage device that can be assumed as the shape of a Gramophone record. This disk is coated on both sides with a thin film of Magnetic material. This magnetic material has the property that it can store either ‘1’ or ‘0] permanently. The magnetic material has square loop hysteresis (curve) which can remain in one out of two possible directions which correspond to binary ‘1’ or ‘0’. Bits are saved in the magnetized surface in marks along concentric circles known as tracks. The tracks are frequently divided into areas known as sectors.In this system, the ...
Read MoreWhat are the basic components of the memory management unit in computer architecture?
In a multiprogramming system, the main memory is broken into two parts as one part for the operating system (resident monitor) ad one part for the program currently being implemented. In a multiprogramming system, the “user” part of memory is divided to contain various processes. The task of the subdivision is carried out dynamically by the operating framework and is called memory management.Address spaces − The Pentium-II contains hardware for both segmentation and paging. Both mechanisms can be disabled, enabling the user to select from the definite aspect of memory −Unsegmented unpaged memory − In this case, the virtual address ...
Read MoreWhat is the difference between Latch and Flip-Flops in computer architecture?
LatchA latch is a device with particularly two stable states and these states are high-output and low-output. A latch has a feedback direction, to maintain the data. Latches can be memory devices and can save one bit of information. It is used to “latch onto” data and save it in the required area. One of the most generally used latches is the SR latch.An SR latch is an asynchronous device. An SR latch does not rely upon control signals but relies only on the state of the S and R inputs. An SR latch can be generated by interlinking two ...
Read MoreWhat are semiconductor-based ROM memories in computer architecture?
Classic mask-programmed ROM chips are joined circuits that physically encode the information to be saved, and therefore it is inaccessible to modify their contents after fabrication. Several methods of non-volatile solid-state memory allow some degree of modification −Programmable read-only memory (PROM) − It is a one-time programmable ROM (OTP) and can be written to or programmed through a unique device known as a PROM programmer. This device uses high voltages to permanently damage or generate internal connections (fuses or anti-fuses) inside the chip.Erasable Programmable read-only memory (EPROM) − It can be erased by hazard to powerful ultraviolet light (generally for ...
Read MoreWhat is Convex Exemplar in computer architecture?
Convex was the first device produce to commercialize a CC-NUMA machine, known as the SPP1000. SPP represents a Scalable Parallel Processor. The goals of the SPP Exemplar series are to make a family of high-implementation computers where the multiple processors can simply range from 10 to 1000 and the peak implementation would arrive at the TeraFLOPS.The node of the SP1000 is symmetric multiprocessors, called hyper nodes. Each hypernode includes four functional blocks and an I/O subsystem. Each functional block includes two CPUs (HP PA-RISCs) sending an individual CPU agent, and a memory unit influencing hypernode private memory data, global memory ...
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