The priority encoder is a circuit that executes the priority function. The logic of the priority encoder is such that two or more inputs appear at an equal time, the input having the largest priority will take precedence. The truth table of a four-input priority encoder is given in the table. The X’s in the table designate don’t care conditions. Input I0 has the largest priority, so indifferent of the values of other inputs when this is input is 1, the output creates an output xy=00.
I1 has the next priority level. The output is 01 if I1=1 supported that I0=0, regardless of the values of the other two lower-priority inputs. The output for I2 is generated only if higher-priority inputs are 0, etc. down the priority level. The interrupt status IST is set only when one or more inputs are equal to 1.
Priority Encoder for the truth table
If all inputs are 0, IST is cleared to 0 and the other outputs of the encoder are not used, so they are signified with don’t care condition. This is because the vector address is not shared with the CPU when IST=0. The Boolean function showed in the table determines the internal logic of the encoder. Generally, a computer will have more than four interrupt sources. A priority encoder with eight inputs, for example, will create an output of three bits.
The output of the priority encoder can form part of the vector address for each interrupt source. The other bits of the vector address can be created any value. For instance, the vector address can be formed by joining six zeroes to the x and y outputs of the encoder. With this choice, the interrupt vector for the four I/O devices is created binary numbers 0, 1, 2, and 3.
The parallel priority interrupt technique uses a register whose bits are set independently by the interrupt signal from each device. Priority is created as per the position of the bits in the register.
In addition to the interrupt register, the circuit can contain a mask register whose objective is to control the status of each interrupt request. The mask register can be programmed to disable lower-priority interrupts while a higher-priority device is being serviced. It also supports a facility that enables a high-priority device to interrupt the CPU while a lower-priority device is being serviced.