In 8085 Instruction set, we are having one mnemonic JPO a16, which stands for “Jump if Parity Odd” and “a16” stands for any 16-bit address. This instruction is used to jump to the address a16 as provided in the instruction. But as it is a conditional jump so it will happen if and only if the present parity flag value is 0. If parity flag value is 1, program flow continues sequentially. It is a 3-Byte instruction.
|Mnemonics, Operand||Opcode(in HEX)||Bytes|
Let us consider one example of this instruction type JPO 4000H. It is a 3-Byte instruction. The result of execution of this instruction is shown below with an example.
|2000||3E||MVI A, 40||A ← 40H|
|2001||40||8-bit operand 40H|
|2002||06||MVI B,30||B ← 30H|
|2003||30||8-bit operand 30H|
|2004||90||SUB B||A ← A – B= 40H – 30H = 10H. As the result is 10H = 0001 000B, so the Pflag bit will be 0|
|2005||E2||JPO 4000||Jump Parity Odd, i.e. Jump when P = 0, as the subtraction result is 10H, so P flag bit will remain with value 0|
|2006||00||Low order Byte of the target address|
|2007||40||High order Byte of the target address|
PC ← 4000H, So the program control will be transferred to the address 4000H
|2008||78||MOV A, B||This instruction will not get control now as JPO will transfer the control to the memory address 4000H|
|4000||41||MOV B, C||Next instruction at address 4000H will get the control|
The timing diagram against this instruction JPO 4000H execution is as follows –
Summary − So this instruction JPO requires 3-Bytes, 3-Machine Cycles (Opcode Fetch, Memory Read, MemoryRead) and 10 T-States for execution as shown in the timing diagram.