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**Multiplexer** is a combinational circuit that has maximum of 2^{n} data inputs, ‘n’ selection lines and single output line. One of these data inputs will be connected to the output based on the values of selection lines.

Since there are ‘n’ selection lines, there will be 2^{n} possible combinations of zeros and ones. So, each combination will select only one data input. Multiplexer is also called as **Mux**.

4x1 Multiplexer has four data inputs I_{3}, I_{2}, I_{1} & I_{0}, two selection lines s_{1} & s_{0} and one output Y. The **block diagram** of 4x1 Multiplexer is shown in the following figure.

One of these 4 inputs will be connected to the output based on the combination of inputs present at these two selection lines. **Truth table** of 4x1 Multiplexer is shown below.

Selection Lines | Output | |
---|---|---|

S_{1} |
S_{0} |
Y |

0 | 0 | I_{0} |

0 | 1 | I_{1} |

1 | 0 | I_{2} |

1 | 1 | I_{3} |

From Truth table, we can directly write the **Boolean function** for output, Y as

$$Y={S_{1}}'{S_{0}}'I_{0}+{S_{1}}'S_{0}I_{1}+S_{1}{S_{0}}'I_{2}+S_{1}S_{0}I_{3}$$

We can implement this Boolean function using Inverters, AND gates & OR gate. The **circuit diagram** of 4x1 multiplexer is shown in the following figure.

We can easily understand the operation of the above circuit. Similarly, you can implement 8x1 Multiplexer and 16x1 multiplexer by following the same procedure.

Now, let us implement the following two higher-order Multiplexers using lower-order Multiplexers.

- 8x1 Multiplexer
- 16x1 Multiplexer

In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer. We know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one output. Whereas, 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output.

So, we require two **4x1 Multiplexers** in first stage in order to get the 8 data inputs. Since, each 4x1 Multiplexer produces one output, we require a **2x1 Multiplexer** in second stage by considering the outputs of first stage as inputs and to produce the final output.

Let the 8x1 Multiplexer has eight data inputs I_{7} to I_{0}, three selection lines s_{2}, s_{1} & s0 and one output Y. The **Truth table** of 8x1 Multiplexer is shown below.

Selection Inputs | Output | ||
---|---|---|---|

S_{2} |
S_{1} |
S_{0} |
Y |

0 | 0 | 0 | I_{0} |

0 | 0 | 1 | I_{1} |

0 | 1 | 0 | I_{2} |

0 | 1 | 1 | I_{3} |

1 | 0 | 0 | I_{4} |

1 | 0 | 1 | I_{5} |

1 | 1 | 0 | I_{6} |

1 | 1 | 1 | I_{7} |

We can implement 8x1 Multiplexer using lower order Multiplexers easily by considering the above Truth table. The **block diagram** of 8x1 Multiplexer is shown in the following figure.

The same **selection lines, s _{1} & s_{0}** are applied to both 4x1 Multiplexers. The data inputs of upper 4x1 Multiplexer are I

The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is present in second stage. The other **selection line, s _{2}** is applied to 2x1 Multiplexer.

If s

_{2}is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I_{3}to I_{0}based on the values of selection lines s_{1}& s_{0}.If s

_{2}is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I_{7}to I_{4}based on the values of selection lines s_{1}& s_{0}.

Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer performs as one 8x1 Multiplexer.

In this section, let us implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1 Multiplexer. We know that 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output. Whereas, 16x1 Multiplexer has 16 data inputs, 4 selection lines and one output.

So, we require two **8x1 Multiplexers** in first stage in order to get the 16 data inputs. Since, each 8x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by considering the outputs of first stage as inputs and to produce the final output.

Let the 16x1 Multiplexer has sixteen data inputs I_{15} to I_{0}, four selection lines s_{3} to s_{0} and one output Y. The **Truth table** of 16x1 Multiplexer is shown below.

Selection Inputs | Output | |||
---|---|---|---|---|

S_{3} |
S_{2} |
S_{1} |
S_{0} |
Y |

0 | 0 | 0 | 0 | I_{0} |

0 | 0 | 0 | 1 | I_{1} |

0 | 0 | 1 | 0 | I_{2} |

0 | 0 | 1 | 1 | I_{3} |

0 | 1 | 0 | 0 | I_{4} |

0 | 1 | 0 | 1 | I_{5} |

0 | 1 | 1 | 0 | I_{6} |

0 | 1 | 1 | 1 | I_{7} |

1 | 0 | 0 | 0 | I_{8} |

1 | 0 | 0 | 1 | I_{9} |

1 | 0 | 1 | 0 | I_{10} |

1 | 0 | 1 | 1 | I_{11} |

1 | 1 | 0 | 0 | I_{12} |

1 | 1 | 0 | 1 | I_{13} |

1 | 1 | 1 | 0 | I_{14} |

1 | 1 | 1 | 1 | I_{15} |

We can implement 16x1 Multiplexer using lower order Multiplexers easily by considering the above Truth table. The **block diagram** of 16x1 Multiplexer is shown in the following figure.

The **same selection lines, s _{2}, s_{1} & s_{0}** are applied to both 8x1 Multiplexers. The data inputs of upper 8x1 Multiplexer are I

The outputs of first stage 8x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is present in second stage. The other **selection line, s _{3}** is applied to 2x1 Multiplexer.

If s

_{3}is zero, then the output of 2x1 Multiplexer will be one of the 8 inputs Is_{7}to I_{0}based on the values of selection lines s_{2}, s_{1}& s_{0}.If s

_{3}is one, then the output of 2x1 Multiplexer will be one of the 8 inputs I_{15}to I_{8}based on the values of selection lines s_{2}, s_{1}& s_{0}.

Therefore, the overall combination of two 8x1 Multiplexers and one 2x1 Multiplexer performs as one 16x1 Multiplexer.

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