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# Digital Circuits - Decoders

**Decoder** is a combinational circuit that has ‘n’ input lines and maximum of 2^{n} output lines. One of these outputs will be active High based on the combination of inputs present, when the decoder is enabled. That means decoder detects a particular code. The outputs of the decoder are nothing but the **min terms** of ‘n’ input variables (lines), when it is enabled.

## 2 to 4 Decoder

Let 2 to 4 Decoder has two inputs A_{1} & A_{0} and four outputs Y_{3}, Y_{2}, Y_{1} & Y_{0}. The **block diagram** of 2 to 4 decoder is shown in the following figure.

One of these four outputs will be ‘1’ for each combination of inputs when enable, E is ‘1’. The **Truth table** of 2 to 4 decoder is shown below.

Enable | Inputs | Outputs | ||||
---|---|---|---|---|---|---|

E |
A_{1} |
A_{0} |
Y_{3} |
Y_{2} |
Y_{1} |
Y_{0} |

0 | x | x | 0 | 0 | 0 | 0 |

1 | 0 | 0 | 0 | 0 | 0 | 1 |

1 | 0 | 1 | 0 | 0 | 1 | 0 |

1 | 1 | 0 | 0 | 1 | 0 | 0 |

1 | 1 | 1 | 1 | 0 | 0 | 0 |

From Truth table, we can write the **Boolean functions** for each output as

$$Y_{3}=E.A_{1}.A_{0}$$

$$ Y_{2}=E.A_{1}.{A_{0}}'$$

$$ Y_{1}=E.{A_{1}}'.A_{0}$$

$$ Y_{0}=E.{A_{1}}'.{A_{0}}'$$

Each output is having one product term. So, there are four product terms in total. We can implement these four product terms by using four AND gates having three inputs each & two inverters. The **circuit diagram** of 2 to 4 decoder is shown in the following figure.

Therefore, the outputs of 2 to 4 decoder are nothing but the **min terms** of two input variables A_{1} & A_{0}, when enable, E is equal to one. If enable, E is zero, then all the outputs of decoder will be equal to zero.

Similarly, 3 to 8 decoder produces eight min terms of three input variables A_{2}, A_{1} & A_{0} and 4 to 16 decoder produces sixteen min terms of four input variables A_{3}, A_{2}, A_{1} & A_{0}.

## Implementation of Higher-order Decoders

Now, let us implement the following two higher-order decoders using lower-order decoders.

- 3 to 8 decoder
- 4 to 16 decoder

### 3 to 8 Decoder

In this section, let us implement **3 to 8 decoder using 2 to 4 decoders**. We know that 2 to 4 Decoder has two inputs, A_{1} & A_{0} and four outputs, Y_{3} to Y_{0}. Whereas, 3 to 8 Decoder has three inputs A_{2}, A_{1} & A_{0} and eight outputs, Y_{7} to Y_{0}.

We can find the number of lower order decoders required for implementing higher order decoder using the following formula.

$$Required \: number \: of \: lower \: order \: decoders=\frac{m_{2}}{m_{1}}$$

Where,

$m_{1}$ is the number of outputs of lower order decoder.

$m_{2}$ is the number of outputs of higher order decoder.

Here, $m_{1}$ = 4 and $m_{2}$ = 8. Substitute, these two values in the above formula.

$$Required \: number \: of \: 2 \: to \: 4 \: decoders=\frac{8}{4}=2$$

Therefore, we require two 2 to 4 decoders for implementing one 3 to 8 decoder. The **block diagram** of 3 to 8 decoder using 2 to 4 decoders is shown in the following figure.

The parallel inputs A_{1} & A_{0} are applied to each 2 to 4 decoder. The complement of input A_{2} is connected to Enable, E of lower 2 to 4 decoder in order to get the outputs, Y_{3} to Y_{0}. These are the **lower four min terms**. The input, A_{2} is directly connected to Enable, E of upper 2 to 4 decoder in order to get the outputs, Y_{7} to Y_{4}. These are the **higher four min terms**.

### 4 to 16 Decoder

In this section, let us implement **4 to 16 decoder using 3 to 8 decoders**. We know that 3 to 8 Decoder has three inputs A_{2}, A_{1} & A_{0} and eight outputs, Y_{7} to Y_{0}. Whereas, 4 to 16 Decoder has four inputs A_{3}, A_{2}, A_{1} & A_{0} and sixteen outputs, Y_{15} to Y_{0}

We know the following formula for finding the number of lower order decoders required.

$$Required \: number \: of \: lower \: order \: decoders=\frac{m_{2}}{m_{1}}$$

Substitute, $m_{1}$ = 8 and $m_{2}$ = 16 in the above formula.

$$Required \: number \: of \: 3 \: to \: 8 decoders=\frac{16}{8}=2$$

Therefore, we require two 3 to 8 decoders for implementing one 4 to 16 decoder. The **block diagram** of 4 to 16 decoder using 3 to 8 decoders is shown in the following figure.

The parallel inputs A_{2}, A_{1} & A_{0} are applied to each 3 to 8 decoder. The complement of input, A3 is connected to Enable, E of lower 3 to 8 decoder in order to get the outputs, Y_{7} to Y_{0}. These are the **lower eight min terms**. The input, A_{3} is directly connected to Enable, E of upper 3 to 8 decoder in order to get the outputs, Y_{15} to Y_{8}. These are the **higher eight min terms**.