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Makefile's Other Features

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Recursive Use of make

Recursive use of make means using make as a command in a makefile. This technique is useful when you want separate makefiles for various subsystems that compose a larger system. For example, suppose you have a subdirectory `subdir' which has its own makefile, and you would like the containing directory's makefile to run make on the subdirectory. You can do it by writing this:
        cd subdir && $(MAKE)

or, equivalently
        $(MAKE) -C subdir

You can write recursive make commands just by copying this example, but there are many things to know about how they work and why, and about how the sub-make relates to the top-level make

Communicating Variables to a Sub-make

Variable values of the top-level make can be passed to the sub-make through the environment by explicit request. These variables are defined in the sub-make as defaults, but do not override what is specified in the makefile used by the sub-make makefile unless you use the `-e' switch

To pass down, or export, a variable, make adds the variable and its value to the environment for running each command. The sub-make, in turn, uses the environment to initialize its table of variable values

The special variables SHELL and MAKEFLAGS are always exported (unless you unexport them). MAKEFILES is exported if you set it to anything.

If you want to export specific variables to a sub-make, use the export directive, like this:

export variable ...

If you want to prevent a variable from being exported, use the unexport directive, like this:

unexport variable ...

The Variable MAKEFILES

If the environment variable MAKEFILES is defined, make considers its value as a list of names (separated by whitespace) of additional makefiles to be read before the others. This works much like the include directive: various directories are searched for those files.

The main use of MAKEFILES is in communication between recursive invocations of make

Header file inclusion from different directories

If you have put your header files in different directories and you arerunning make in different directory then it is required to tell the path of header files. This can be done using -I option in makefile. Assuming that functions.h file is available in /home/tutorialspoint/header and rest of the files are available in /home/tutorialspoint/src/ then make file would be written as follows.
INCLUDES = -I "/home/tutorialspoint/header"
CC = gcc
LIBS =  -lm
CFLAGS = -g -Wall
OBJ =  main.o factorial.o hello.o

hello: ${OBJ}
   ${CC} ${CFLAGS} ${INCLUDES} -o $@ ${OBJS} ${LIBS}
   ${CC} ${CFLAGS} ${INCLUDES} -c $<

Appending More Text to Variables

Often it is useful to add more text to the value of a variable already defined. You do this with a line containing `+=', like this:

objects += another.o

This takes the value of the variable objects, and adds the text `another.o' to it (preceded by a single space). Thus:

objects = main.o hello.o factorial.o
objects += another.o

sets objects to `main.o hello.o factorial.o another.o'.

Using `+=' is similar to:

objects = main.o hello.o factorial.o
objects := $(objects) another.o

Continution Line in Makefile

If you don't like too big lines in your Makefile then you can break your line using a back-slash "\" as shown below

OBJ =  main.o factorial.o \

is equivalent to

OBJ =  main.o factorial.o hello.o

Running Makefile from command prompt

If you have prepared yur Makefile with a name as "Makefile" then simply write make at command prompt and it will run your Makefile file. But if you have given any other name to your Makefile then use the following command

make -f your-makefile-name

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